During wafer processing, the backside of the wafers is sometimes contaminated with metallic contamination by the wafer handling tools. The metallic contamination on the wafer backside is then driven deeper into the wafer during subsequent annealing or higher temperature processes. Further, during the Cl2 recess cSiGe process for positive field-effect transistors (PFETs) in a standard vertical processing furnace, metallic contamination can be released from the wafer backside and deposited onto the front side of the wafer sitting below, which then can increase the etch rate of silicon (Si) and cause hole defects in the PFET during the epitaxy growth process. In addition, available standard cleaning (SC-1, SC-2) procedures, are ineffective in this context because the metallic contamination has already been driven into the silicon backside prior to the recess process.
A need therefore exists for methodology and apparatus enabling fabrication of semiconductor devices having Cl2 recessed cSiGe with reduced hole defects.